The Switch Flashcart Thread (Mig Switch/UnlockSwitch etc.)

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gbadl

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csab6482 said:
The v2 flashcart I most recently got in has some differences compared to the initial release of the v2. I guess we can call this new one v2.1 and I will focus on redesigning my PCB around this one as it has some good improvements, namely with moving some capacitors and resistors off of far edges of the board. In the attached photos the v2 is on the left and v2.1 is on the right.View attachment 472275View attachment 472276
Click to expand...
By any chance did open mig ever get back to you about a open firmware?
 
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csab6482

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gbadl said:
By any chance did open mig ever get back to you about a open firmware?
Click to expand...
I was unable to reach either them or UnlockSwitch via Twitter DM, and given my thoughts in post #1700 I am considering the firmware from either team to be snake oil until they can prove otherwise. As little as a picture of their IDE would make me believe that they are at least working on it.

Also, I've updated the GH repository to the newer version of the Flashcart - https://github.com/sabogalc/MIG-Flash-PCBs
Post automatically merged:

For anyone that knows how to work with software, I tried to prompt ChatGPT for assistance with writing a firmware for the Dumper board. Below is the response. I've also attached an example code file that it gave me.

To assist you in writing the firmware for the ESP32-S2 MCU that will allow your board to function correctly, we'll need to address several key areas:


  1. Understanding the Role of Each Component in Your System
  2. Establishing Communication Between the ESP32-S2 and the FPGA
  3. Programming the FPGA Using the ESP32-S2
  4. Implementing the Cartridge Communication Protocol
  5. Facilitating Data Transfer Over USB

Let's break down each of these steps to provide a clear path forward.




1. Understanding the Role of Each Component in Your System​


Components and Their Roles:


  • Memory Cartridge: Provides data using a custom SPI-like protocol over an 8-bit data bus.
  • iCE40 UltraPlus FPGA: Acts as a bridge, translating the cartridge's communication protocol to standard SPI.
  • ESP32-S2 MCU: Programs the FPGA and may handle additional data processing or communication tasks.
  • SD to USB Chip: Converts SD card interface signals to USB, enabling data to be read over USB.

System Workflow:


  1. The cartridge communicates with the FPGA using its custom protocol.
  2. The FPGA translates this protocol to standard SPI.
  3. The FPGA communicates the data to both the ESP32-S2 MCU and the SD to USB chip.
  4. The SD to USB chip allows the data to be accessed over USB.



2. Establishing Communication Between the ESP32-S2 and the FPGA​


Pin Connections Between ESP32-S2 and FPGA:


  • Programming Pins:
    • CRESET (FPGA Reset): Connected to GP5 of the ESP32-S2.
    • CDONE (Configuration Done): Connected to GP6 of the ESP32-S2.
  • SPI Interface Pins:
    • SPI_SO (Slave Out): Connected to GP13.
    • SPI_SI (Slave In): Connected to GP11.
    • SPI_SCK (Clock): Connected to GP12.
    • SPI_SS (Chip Select): Connected to GP10.

Steps to Establish Communication:


  1. Configure GPIO Pins:
    • Set up GP5 as an output to control CRESET.
    • Set up GP6 as an input to monitor CDONE.
  2. Initialize SPI Interface:
    • Use the ESP32-S2's SPI master driver to set up SPI communication on the specified pins.
    • Configure SPI parameters (mode, clock speed, etc.) compatible with the FPGA's requirements.



3. Programming the FPGA Using the ESP32-S2​


FPGA Configuration Steps:


  1. Hold FPGA in Reset:
    • Drive CRESET (connected to GP5) low to reset the FPGA.
  2. Prepare for Configuration:
    • Ensure SPI_SS (Chip Select) is high.
    • Initialize the SPI interface.
  3. Release FPGA from Reset:
    • Drive CRESET high to start the configuration process.
  4. Load Bitstream:
    • Send the FPGA configuration bitstream over SPI.
    • The bitstream can be stored in the ESP32-S2's flash memory or fetched over a network if connected.
  5. Monitor Configuration Status:
    • Read CDONE (connected to GP6) to verify successful configuration.

Implementing the Configuration in Firmware:


  • SPI Communication:
    • Use the ESP-IDF's SPI master driver to handle data transmission.
    • Send the bitstream in chunks, ensuring adherence to timing requirements.
  • Error Handling:
    • Implement checks for configuration errors.
    • Retry configuration if CDONE does not indicate success.



4. Implementing the Cartridge Communication Protocol​


Understanding the Protocol:


  • SPI-like Bus with 8-bit Width:
    • Data lines DAT7..0.
    • Commands are 16 bytes, followed by a 4-byte CRC-32.
  • Communication Flow:
    • Host (FPGA) initiates transfer by pulling CS low.
    • Commands are sent, followed by CRC.
    • Bus direction changes implicitly; cartridge responds.
    • Cartridge sends acknowledgment and response data, followed by CRC.

Implementing Protocol Translation in FPGA:


  • FPGA Responsibilities:
    • Translate the cartridge's SPI-like protocol to standard SPI.
    • Communicate with the SD to USB chip and potentially the ESP32-S2.
  • ESP32-S2's Role (If Any):
    • If the FPGA requires commands or data from the ESP32-S2 during operation, implement a communication protocol (e.g., SPI, I2C, UART) between them.
    • If the ESP32-S2 is to process or forward data, handle the data accordingly.



5. Facilitating Data Transfer Over USB​


Options for USB Communication:


  1. Using the SD to USB Chip:
    • Since the SD to USB chip is connected to the FPGA and designed to interface over USB, the primary data transfer can occur through this chip.
    • No additional firmware on the ESP32-S2 is required for basic USB functionality in this case.
  2. Using the ESP32-S2 as a USB Device (Optional):
    • The ESP32-S2 has built-in USB OTG capabilities.
    • You can implement USB device functionality in the ESP32-S2 to provide additional features or interfaces.

Implementing USB Communication in Firmware (If Needed):


  • Using ESP-IDF USB Stack:
    • Initialize the USB peripheral using the ESP-IDF USB library.
    • Implement USB classes (e.g., CDC, MSC, HID) as per your application's requirements.
  • Data Handling:
    • If the ESP32-S2 is to act as a USB mass storage device or any other USB class, implement the necessary protocols.
    • Ensure data integrity and proper synchronization with the FPGA.



Putting It All Together: Step-by-Step Guide​


  1. Set Up the Development Environment:
    • Install the latest version of ESP-IDF for the ESP32-S2.
    • Install necessary toolchains and drivers.
  2. Create a New ESP-IDF Project:
    • Use the idf.py tool to create and manage your project.
  3. Configure GPIOs and SPI Interface:
    • Define GPIO numbers for CRESET, CDONE, and SPI pins in your code.
    • Initialize the GPIO and SPI peripherals in your app_main() function.
  4. Implement FPGA Programming Logic:
    • Write functions to control CRESET and monitor CDONE.
    • Write a function to load the FPGA bitstream over SPI.
  5. Store and Access the FPGA Bitstream:
    • Add the FPGA bitstream file to your project's file system (e.g., SPIFFS, FATFS).
    • Use file I/O APIs to read the bitstream data during programming.
  6. Handle Errors and Edge Cases:
    • Implement timeouts and retries for the FPGA programming process.
    • Log error messages using the ESP-IDF logging system.
  7. Test the FPGA Programming:
    • Connect your hardware and flash the firmware to the ESP32-S2.
    • Use debugging tools (e.g., serial console, logic analyzer) to verify signals.
  8. Implement Additional Communication (If Required):
    • If the ESP32-S2 needs to communicate with the FPGA post-configuration, implement the necessary protocols.
    • Ensure synchronization between the ESP32-S2 and FPGA for data integrity.
  9. Implement USB Functionality (Optional):
    • If you choose to use the ESP32-S2's USB capabilities, initialize the USB stack.
    • Implement the desired USB class and handle data transfer appropriately.



Additional Tips and Resources​


  • Consult FPGA Documentation:
    • Review the Lattice iCE40 UltraPlus FPGA documentation for details on the SPI configuration protocol.
    • Pay attention to timing requirements and signal integrity considerations.
  • Leverage Example Projects:
    • Look for example projects or existing code that demonstrates FPGA programming over SPI using an MCU.
    • Adapt relevant portions to your project.
  • Use the ESP32 Community:
    • The ESP32 community forums and GitHub repositories are valuable resources for troubleshooting and guidance.
  • Debugging:
    • Use an oscilloscope or logic analyzer to monitor SPI signals and ensure correct operation.
    • Implement verbose logging to aid in debugging issues during development.



Summary​


To proceed with your project:


  1. Program the FPGA using the ESP32-S2 via SPI.
  2. Ensure the FPGA correctly translates the cartridge protocol to SPI.
  3. Allow the SD to USB chip to handle USB communication, or implement USB functionality on the ESP32-S2 if additional features are needed.

By following these steps and utilizing the resources provided, you'll be well on your way to developing the firmware needed to make your board operational.
 

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alepolo101

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Hey everyone!
Is there a full consensus yet on what actually fully gets you banned? Does using a fully private dump on 2 switches at once certainly cause a ban or was that just speculation? If I don’t use one of the mega torrents and dump the games myself, even if they’re shared only among 2-3 people there’s a chance we might both accidentally launch the game at the same time.

Does consensus think that that causes a ban? Or just using flagged certificates that are being used by probably thousands of people?
 
TheStonedModder

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alepolo101 said:
Hey everyone!
Is there a full consensus yet on what actually fully gets you banned? Does using a fully private dump on 2 switches at once certainly cause a ban or was that just speculation? If I don’t use one of the mega torrents and dump the games myself, even if they’re shared only among 2-3 people there’s a chance we might both accidentally launch the game at the same time.

Does consensus think that that causes a ban? Or just using flagged certificates that are being used by probably thousands of people?
Click to expand...
A buddy and mine have been sharing our own personal libraries and playing with each other since the mig was released

It’s fine as long as your dumps are 100% private
 

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