Hardware How Does NAND Hardware ECC Work?

[gudenau]

According to the Wiki the NAND hardware ECC is formated like this:

Which translates to something like this structure:

typedef struct{
    uint8_t spare[0x40];
    uint8_t ecc[0x10];
} NandECC;

which is easy enough to understand.

What I don't know is how that gets calculated by the NAND hardware. It says that the 0x10 bytes after the spare data is calculated by the NAND engine,

How is this calculated and how can the ECC data be used? The wiki does not seem to have any info about this.

 

[GerbilSoft]

ECC implementations vary from device to device. I'm not sure about how the Wii's NAND chip implements it, but here's an example for TI devices: http://processors.wiki.ti.com/index.php/Raw_NAND_ECC