I suggest you read a GBA CPU implementation in verilog and how it works, because it runs on the wire level. There you should get all your answers.
(thanks nocash again, lol)
Anyway, the GPIO on the GBA is custom, the AGB CPU has an address decoder in the CPU itself. That's where all the magic happens. The above Signal Summary is the address decoding wired to each GBA CPU pin, and where it targets to. In this case, we refer to the "Cart Bus" data lines.
Cart Bus + GPIO scheme:
Ports C4, C6, C8 through the address decoder, change the data lines between ROM and onboard GPIO (D0-D7) on the GBA cartridge. So what you should be reading, is not the FlashROM docs, but how the FlashROM is wired to GPIO.
2 wires are important here (IIRC it was A14-A15) connected to GBA Cartridge, one being the Flash ROM and the other a GENERAL PURPOSE pin. 2 wires make up for: 0 = FlashROM (ROM mapped to AGB) / GPIO0, 1 = FlashROM (ROM mapped to AGB) / GPIO 1, 2 = FlashROM (ROM mapped to AGB) / GPIO 2, 3 = FlashROM (ROM mapped to AGB) / GPIO 3.
That's why you get setups like this:
And then each GP Pin is connected to RTC, gyroscope, whatever. And I meant by tristate power, because the AGB address decoder is a tri-state inverter. An inverter can tristate power from a data line. Case use would be accessing the FlashROM from the AGB CPU, otherwise you'd need the FlashROM circuitry to eat absurd ammounts of battery life unnecessarily.
TLDR: GPIO is parallel to FlashROM by having different data lines, but get's mapped to the same GBA io port through the address decoder.
Hey thanks so much! It's nice to find someone that has this knowledge that seems so rare. I hope to learn as much as I can!
Is there a verilog implementation of the game boy advance? All I could "find" was the original game boy and not the game boy advance.
I think I got the wire configuration from the CPU to Cart Bus to ROM Chip to RTC Chip down:
ROM Address C8h & AGB CPU GPIO Enable/Disable Register
GBA Address: 80000C8h
ROM Address: C8h = 11001000b
MX23L6407-12C ROM Chip Pins: 14, 17, 28 @ 3.3 V remainder address lines @ GND
Cart Bus Pins: 9 [AD3], 12 [AD6], 13 [AD7] @ 3.3 V remainder address lines @ GND
CPU AGB Pins: 30, 27, 26 @ 3.3 V remainder of cart bus address lines @ GND
ROM Address C6h & AGB CPU Data Direction Register
GBA Address: 800006h
ROM Address: C6h = 11000110b
MX23L6407-12C ROM Chip Pins: 11, 12, 17, Pin 28 @ 3.3 V remainder address lines @ GND
Cart Bus Pins: 7 [AD1], 8 [AD2], 12 [AD6], 13 [AD7] @ 3.3 V remainder address lines @ GND
CPU AGB Pins: 32, 31, 27, 26 @ 3.3 V remainder of cart bus address lines @ GND
ROM Address C4h & CPU GPIO Data Register
GBA Address 80000C4h
ROM Address C4h = 11000100b
MX23L6407-12C ROM Chip Pins: 12, 17, 28 @ 3.3 V remainder of address lines @ GND
Cart Bus Pins: 8 [AD2], 12 [AD6], 13 [AD7] @ 3.3 V remainder address lines @ GND
CPU AGB Pins: 31, 27, 26 @ 3.3 V remainder of cart bus address lines @ GND
RTC 341055 to ROM Chip Interface
3 Wire SPI is used over GPIO pins, so bit banging is being used
341055 Pin 1 [INT] = MX23L6407-12C ROM Chip Pin 44 [IRQ]
341055 Pin 5 [CS] = MX23L6407-12C ROM Chip Pin 21 [CS]
341055 Pin 6 [SCK] = MX23L6407-12C ROM Chip Pin 1 [SCK]
341055 Pin 7 [SIO] = MX23L6407-12C ROM Chip Pin 2 [SIO]
I can't find any datasheet what so ever on the ROM chip, MX23L6407-12C. Even when I look at the manufacturers website, they don't have anything listed for this part, but for similar ones that aren't used in Nintendo carts. I can't find any documentation on the ROM chip to GPIO interface. Which I suspect is in the datasheet.
Were I'm struggling to understand is this:
- Addresses C4, C6 and C8 have data stored on the ROM that is read from
- Addresses C4, C6 and C8 are ALSO used for GPIO data
- There appears to be some custom logic that is within the ROM Chip to switch between ROM data and GPIO data
- The RTC chip is connected to the ROM chip ONLY, so the switching logic MUST be in the ROM chip
- What is the logic that causes this switch to occur?
This I really don't understand. I can't wrap my brain around it. It seems to
I think it's this but I'm not entirely sure.
I think the key lies in address C8.
It would seem that you write the data 0000000000001111 at address C8 to switch from ROM data to GPIO data on all 4 GPIO pins.
You then write 0000000000000000 at address C8 to switch back to ROM data
Interesting, that I did not know! The GPIO data is on the same lines as the 8 bit data for SRAM, Cart Bus Pins 22 [D0] through Pin 27 [D7]? Is this right? This doesn't seem to match up with GBATEK which has the GPIO data as 16 bits and not 8 bits.
Although this begs the question, why are the 8 bits of data for flash storage to save games connected to both the ROM Chip that stores the actual game AND the flash chip to save games? I would expect no interaction between the two chips. Btu something is clearly going on here.