FWIW, a full SMP port of Linux is probably not possible given only the information that I disclosed. However, any effort to start and get to a partial port (and subsequently identify what's missing) would already be a big milestone and a demonstration of interest.
marcan-san, I've been diligently working on such an implementation, though most of it has been happening behind-the-scenes.
I will be up front with you, I am absolutely terrible at programming. That said, I have a strong Linux background and figured I would see what I could do.
My preliminary test was successful, basically following the gc-linux wiki to the 'T' and building an SD card from scratch, I was able to boot 2.6.32-mikep5 using HBC.
Then I discovered another project (https://github.com/DeltaResero/GC-Wii-Linux-Kernel-3.0.y) which I tried to build as per the instructions, but alas, the vWii simply would not boot the zImage (result was black screen, though I did not personally test, so I can't say it wasn't user error).
At this point I'm back to vanilla linux-2.6.32 from kernel.org. Applied MIKE's latest patch, and built successfully, just waiting for my tester to get back to me on that for results. Once I've finalized the proper build process for cross-compiling this kernel for PPC, I would like to experiment with enabling SMP in the kernel config, currently CONFIG_SMP is not set.
My question to you is, could enabling SMP in the kernel at least 'show' us more of the CPU (for instance in a cat /proc/cpuinfo)? or does the IOS first have to be modified to extend that boundary.
I'm sorry if this isn't making very much sense. Honestly trying to learn as I go (never owned a Wii) and a lot of trial and error is involved.
Your feedback is appreciated. Thanks
EDIT: further on this, I found this little snippet of code in arch/powerpc/boot/dts/wii.dts. Could modifying these values do anything for us?
Code:
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,gekko@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <486000000>; /* 486MHz */
+ bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */
+ timebase-frequency = <40500000>; /* 162MHz / 4 */
+ /* Following required by dtc but not used */
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ };
+ };