What the actual fuck
--------------------- MERGED ---------------------------
#include "dma_core.hpp"
#include "../bus.hpp
#include "../gpu/gpu_core.hpp"
static dam::state_t state;
static void update_irq_active_flag() {
auto forced = ((state.dicr >> 15) & 1) != 0;
auto master = ((state.dicr >> 23) & 1) != 0;
auto signal = ((state.dicr >> 16) & (state.dicr >> 24) & 0x7f) != 0;
auto active = forced || (master && signal);
if (active) {
if (!(state.dicr & 0x80000000)) {
bus::irq(3);
}
state.dicr |= 0x80000000
} else {
state.dicr &= ~0x80000000;
}
}
static uint32_t get_channel_index(uint32_t address) {
return (address >> 4) & 7;
}
static uint32_t get_channel_index(uint32_t address) {
return (address >> 2) & 3;
}
uint32_t dma::bus_read(int width, uint32_t address) {
auto channel = get_channel_index(address);
if (channel == 7) {
switch (get_register_index(address)) {
case 0: return state.dpcr;
case 1: return state.dicr;
case 2: return 0x7ffac68b;
case 3: return 0x00fffff7;
}
}
else {
switch (get_register_index(address)) {
case 0: return state.channels[channel].address;
case 1: return state.channels[channel].counter;
case 2: return state.channels[channel].control;
}
}
return 0;
}
void dma::bus_write(int width, uint32_t address, uint32_t data) {
auto channel = get_channel_index(address);
if (channel == 7) {
switch (get_register_index(address)) {
case 0: state.dpcr = data; break;
case 1:
state.dicr &= ( 0xff000000);
state.dicr |= (data & 0x00ff803f);
state.dicr &= ~(data & 0x7f000000);
update_irq_active_flag();
break;
case 2: break;
case 3: break;
}
}
else {
switch (get_register_index(address)) {
case 0: state.channels[channel].address = data & 0x00ffffff; break;
case 1: state.channels[channel].counter = data & 0xffffffff; break;
#include "../bus.hpp
#include "../gpu/gpu_core.hpp"
static dam::state_t state;
static void update_irq_active_flag() {
auto forced = ((state.dicr >> 15) & 1) != 0;
auto master = ((state.dicr >> 23) & 1) != 0;
auto signal = ((state.dicr >> 16) & (state.dicr >> 24) & 0x7f) != 0;
auto active = forced || (master && signal);
if (active) {
if (!(state.dicr & 0x80000000)) {
bus::irq(3);
}
state.dicr |= 0x80000000
} else {
state.dicr &= ~0x80000000;
}
}
static uint32_t get_channel_index(uint32_t address) {
return (address >> 4) & 7;
}
static uint32_t get_channel_index(uint32_t address) {
return (address >> 2) & 3;
}
uint32_t dma::bus_read(int width, uint32_t address) {
auto channel = get_channel_index(address);
if (channel == 7) {
switch (get_register_index(address)) {
case 0: return state.dpcr;
case 1: return state.dicr;
case 2: return 0x7ffac68b;
case 3: return 0x00fffff7;
}
}
else {
switch (get_register_index(address)) {
case 0: return state.channels[channel].address;
case 1: return state.channels[channel].counter;
case 2: return state.channels[channel].control;
}
}
return 0;
}
void dma::bus_write(int width, uint32_t address, uint32_t data) {
auto channel = get_channel_index(address);
if (channel == 7) {
switch (get_register_index(address)) {
case 0: state.dpcr = data; break;
case 1:
state.dicr &= ( 0xff000000);
state.dicr |= (data & 0x00ff803f);
state.dicr &= ~(data & 0x7f000000);
update_irq_active_flag();
break;
case 2: break;
case 3: break;
}
}
else {
switch (get_register_index(address)) {
case 0: state.channels[channel].address = data & 0x00ffffff; break;
case 1: state.channels[channel].counter = data & 0xffffffff; break;
