Hacking Stopping the DSTwo CPU?

[spinal_cord]

Is it possible to stop/start the DSTwo CPU at all? I was thinking it would be useful in certain circumstances when there is nothing happening, like in a text reader of image viewer, so that less power is being used.

 

[Schicksalsheld]

So far as i know, the CPU must run ever, you could underclock it or use the lowest Mode.

 

[DSman59]

I guess if the CPU was stopped when using DSTwo plug-ins, then they would hang up so it must work all the time.

 

[Pate]

Well, you could experiment what happens with the MIPS32 "WAIT" opcode, but it is likely that the DSTwo interface hangs if you do that.

I plan to test this at some point, but feel free to try yourself first. :-)

Format: WAIT
Purpose: Enter Standby Mode
Wait for Event
Description:
The WAIT instruction performs an implementation-dependent operation, usually involving a lower power mode.
Software may use bits 24:6 of the instruction to communicate additional information to the processor, and the processor
may use this information as control for the lower power mode. A value of zero for bits 24:6 is the default and must
be valid in all implementations.
The WAIT instruction is typically implemented by stalling the pipeline at the completion of the instruction and entering
a lower power mode. The pipeline is restarted when an external event, such as an interrupt or external request
occurs, and execution continues with the instruction following the WAIT instruction. It is implementation-dependent
whether the pipeline restarts when a non-enabled interrupt is requested. In this case, software must poll for the cause
of the restart.The assertion of any reset or NMI must restart the pipeline and the corresponding exception must be
taken.
If the pipeline restarts as the result of an enabled interrupt, that interrupt is taken between the WAIT instruction and
the following instruction (EPC for the interrupt points at the instruction following the WAIT instruction).

Pate

 

[loby]

The SC has released a library which could make ds2 cpu to idle state.
It will lower power consumption.

library of entering idle in ds2sdk

 

[Pate]

Ok, thanks! I'm just wondering why do they have to make things so difficult, couldn't they just have shown a small source snippet that would do that?

I dumped the library and tried to decipher it, this is what I came up with:

CODE00000000 :
ÂÂ 0:ÂÂÂÂ3c05b000 ÂÂÂÂluiÂÂÂÂa1,0xb000
ÂÂ 4:ÂÂÂÂ3c04b301 ÂÂÂÂluiÂÂÂÂa0,0xb301
ÂÂ 8:ÂÂÂÂ34a60010 ÂÂÂÂoriÂÂÂÂa2,a1,0x10
ÂÂ c:ÂÂÂÂ34840080 ÂÂÂÂoriÂÂÂÂa0,a0,0x80
ÂÂ10:ÂÂÂÂ8cc70000 ÂÂÂÂlwÂÂÂÂa3,0(a2)ÂÂÂÂÂÂÂÂorig_CPM_CPPCR = CPM_CPPCR; (Power Control Register?)
ÂÂ14:ÂÂÂÂ8c880000 ÂÂÂÂlwÂÂÂÂt0,0(a0)ÂÂÂÂÂÂÂÂorig_EMC_DMCR = EMC_DMCR; (DRAM Control Register)
ÂÂ18:ÂÂÂÂ3c020200 ÂÂÂÂluiÂÂÂÂv0,0x200
ÂÂ1c:ÂÂÂÂ01021025 ÂÂÂÂorÂÂÂÂv0,t0,v0
ÂÂ20:ÂÂÂÂac820000 ÂÂÂÂswÂÂÂÂv0,0(a0)ÂÂÂÂÂÂÂÂEMC_DMCR = orig_EMC_DMCR | 0x02000000;
ÂÂ24:ÂÂÂÂ34a50004 ÂÂÂÂoriÂÂÂÂa1,a1,0x4
ÂÂ28:ÂÂÂÂ24020004 ÂÂÂÂliÂÂÂÂv0,4
ÂÂ2c:ÂÂÂÂ34e30200 ÂÂÂÂoriÂÂÂÂv1,a3,0x200
ÂÂ30:ÂÂÂÂacc30000 ÂÂÂÂswÂÂÂÂv1,0(a2)ÂÂÂÂÂÂÂÂCPM_CPPCR = orig_CPM_CPPCR | 0x0200;
ÂÂ34:ÂÂÂÂaca20000 ÂÂÂÂswÂÂÂÂv0,0(a1)ÂÂÂÂÂÂÂÂCPM_LCR = 4;
ÂÂ38:ÂÂÂÂacc70000 ÂÂÂÂswÂÂÂÂa3,0(a2)ÂÂÂÂÂÂÂÂCPM_CPPCR = orig_CPM_CPPR;
ÂÂ3c:ÂÂÂÂac880000 ÂÂÂÂswÂÂÂÂt0,0(a0)ÂÂÂÂÂÂÂÂEMC_DMCR = orig_EMC_DMCR;
ÂÂ40:ÂÂÂÂ03e00008 ÂÂÂÂjrÂÂÂÂra
ÂÂ44:ÂÂÂÂ00000000 ÂÂÂÂnop

The register names are from JZ4740.h, I haven't looked at the data sheets to see what exactly those registers do.

Pate

 

[spinal_cord]

according to the note in tcm.h it seems that it only idles until the next second. does that mean that the DStwo would be continuously ramping between 0 and [enter current clock setting here] and back again, I always thought doing that sort of thing used up more power than just leaving it switched on?