Need some help (VLSI digital circuits)

ThoD

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Didn't know where to put this thread so I put it in this section.

Gotta design some logic gates on Microwind for tomorrow and I'm stuck at the damn stick diagrams. I THINK I've got them right, but I suck at those and the auto-compiled gates won't cut it, so I have to make my own. Can someone help me out a bit? These are the gates I gotta make:

F1= (((A∙B)+C) ∙D)'
F2= ((A∙B)+(C∙D))'
F3= (A+B)+(C∙D)
F4= A+B+C
F5= A∙B∙C
F6= (A∙B)+(C∙D)

I've made the stick diagrams myself, but there will almost definitely be something wrong in at least 1-2 places, so I need something correct to compare them to and see what I have wrong before going ahead to design them on Microwind...

PS: I hate those diagrams:glare:
 

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There are likely better places to ask this, https://electronics.stackexchange.com/ being a start. Most of the people around here into electrical engineering enough to be able to reasonably answer that question, not the highest number likely to be floating by to answer this in a reasonable time, are likely either having flashbacks to doing this in a similar course (and maybe not much since -- this sort of thing tending to be taught either to help them program FPGAs better or as the general "understand the level above what you will be using every day" sort of thing) or about to start on a "in my day we only had SPICE and were glad of it" type spiel. In my case have not really had enough people have troubles enough here that I can suggest a good way to work through it... everybody I have seen had transistors taken up through logic gates so it was not a logical disconnect then logic gates then had to become transistors (or the materials thereof) again. Also in my case I would be lying to say I had not just rapid speeded through https://www.slideshare.net/hhkamat/vlsi-stic-daigram-jce as a refresher.

"and the auto-compiled gates won't cut it, so I have to make my own"
Various questions.
Are you being tested on minimal transistor count or anything fun like preferring one type of transistor (or complementary gate types)? If not for the former then as a thought exercise for yourself then maybe do one of those all NAND setups. Were this normal logic it might add to the mental load but for stick diagrams it could have the reverse effect as you are only really tying inputs and serialising a few. Will suck for lamda based rules but let us not go there for now. Equally if push comes to shove then you have something which works to squeak by for this exercise and can then go back to learn it properly.
Also while most auto whatever programs are not so hot they should be good enough for at most four input gate setups without even the fun of XOR to get in there and complicate things. Do an autogen for those and really drill down into them so you understand them. It might be cheating to hand those in as answers to your exercise but not as a learning exercise for yourself.

The apostrophe at the end is your way of signifying it is NOT operation? Used overbar and proper typesetting for so long I had almost forgotten that one.
Are you going to have to modify them into something like we see in the real world with one of the legs providing an inverse just for fun? I know in the case of F2 that is going to be easy enough if you are just going to NOT the entire output of the bracketed section rather than playing with each of the inputs but this is possibly one of those "teaching moments" similar to them teaching factorial numbers as a back door into teaching recursion. F6 being what it is says much here. Similarly do note that in F3 A and B are ORed unlike in F2 and F6.
If your teachers are horrible this will be a lead in to some kind of circuit timings/circuit hazard segment.
Slightly less horrible but more useful is many of those are similar enough you can probably break them into stages and thus be told to merge them all into one mega gate array.

Anyway it has gone midnight here so no fiddling with this sort of thing from me.
 

ThoD

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There are likely better places to ask this, https://electronics.stackexchange.com/ being a start. Most of the people around here into electrical engineering enough to be able to reasonably answer that question, not the highest number likely to be floating by to answer this in a reasonable time, are likely either having flashbacks to doing this in a similar course (and maybe not much since -- this sort of thing tending to be taught either to help them program FPGAs better or as the general "understand the level above what you will be using every day" sort of thing) or about to start on a "in my day we only had SPICE and were glad of it" type spiel. In my case have not really had enough people have troubles enough here that I can suggest a good way to work through it... everybody I have seen had transistors taken up through logic gates so it was not a logical disconnect then logic gates then had to become transistors (or the materials thereof) again. Also in my case I would be lying to say I had not just rapid speeded through https://www.slideshare.net/hhkamat/vlsi-stic-daigram-jce as a refresher.

"and the auto-compiled gates won't cut it, so I have to make my own"
Various questions.
Are you being tested on minimal transistor count or anything fun like preferring one type of transistor (or complementary gate types)? If not for the former then as a thought exercise for yourself then maybe do one of those all NAND setups. Were this normal logic it might add to the mental load but for stick diagrams it could have the reverse effect as you are only really tying inputs and serialising a few. Will suck for lamda based rules but let us not go there for now. Equally if push comes to shove then you have something which works to squeak by for this exercise and can then go back to learn it properly.
Also while most auto whatever programs are not so hot they should be good enough for at most four input gate setups without even the fun of XOR to get in there and complicate things. Do an autogen for those and really drill down into them so you understand them. It might be cheating to hand those in as answers to your exercise but not as a learning exercise for yourself.

The apostrophe at the end is your way of signifying it is NOT operation? Used overbar and proper typesetting for so long I had almost forgotten that one.
Are you going to have to modify them into something like we see in the real world with one of the legs providing an inverse just for fun? I know in the case of F2 that is going to be easy enough if you are just going to NOT the entire output of the bracketed section rather than playing with each of the inputs but this is possibly one of those "teaching moments" similar to them teaching factorial numbers as a back door into teaching recursion. F6 being what it is says much here. Similarly do note that in F3 A and B are ORed unlike in F2 and F6.
If your teachers are horrible this will be a lead in to some kind of circuit timings/circuit hazard segment.
Slightly less horrible but more useful is many of those are similar enough you can probably break them into stages and thus be told to merge them all into one mega gate array.

Anyway it has gone midnight here so no fiddling with this sort of thing from me.
To answer quickly since I barely have some time to nap now so I'm not dead tomorrow, I need to make the gates with specific dimensions (eg: x λ horizontally and n λ vertically) and the auto-compiled gates are too long, so modifying them is a pain. What I made the thread for is to ask for someone to make one or two of the stick diagrams I'll need for the gates so I can compare them to mine to make sure I have them correct before I got ahead and make the gates, although I've already made half of them by now:P Finally, yes, the " ' " at the end is a NOT gate attached at the exit node.
 

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