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So, I'm trying to port a CheatEngine cheat table code to the Switch version of the game, and found out that the 2 opcodes that revolve around the cheat need to be converted to 2 or 3 opcodes EACH for the Switch. The problem I am having is figuring out how the switch does a store instruction of an immediate value to the address pointed to by a register PLUS an immediate value, like the below:
str 0x3DA3D70A, [w1 + 0x00000330]
The above code isn't valid, presumably because I formatted it wrong, so I am trying to get the hexadecimal representation of this. I have found an article for Cortex A-series CPUs online, which mentions the possibility of placing an immediate value into an address using store opcodes, but looking at other instruction set lists, I cannot find an opcode that does it. The closest that does anything like it doesn't allow any immediate values whatsoever, only using straight registers. I for certain need at least either an immediate value to be stored or an immediate value to be added to the destination address register. Is there no way to get that? If not, making this code could very well be a pipe dream for me without using IDA Pro or Ghidra on the executable and trying to search for specific instruction patterns, because if I have to split this instruction into more than 2 opcodes, it is unlikely that they will be consecutive in the executable. @FAST6191 I saw your post regarding AArch64 ASM from 2022 in the Vita section, maybe you could weigh in? You seem to know your stuff.
P.S.: The 2 x86 opcodes that I am trying to convert are the following:
Their hexadecimal representation is the following:
str 0x3DA3D70A, [w1 + 0x00000330]
The above code isn't valid, presumably because I formatted it wrong, so I am trying to get the hexadecimal representation of this. I have found an article for Cortex A-series CPUs online, which mentions the possibility of placing an immediate value into an address using store opcodes, but looking at other instruction set lists, I cannot find an opcode that does it. The closest that does anything like it doesn't allow any immediate values whatsoever, only using straight registers. I for certain need at least either an immediate value to be stored or an immediate value to be added to the destination address register. Is there no way to get that? If not, making this code could very well be a pipe dream for me without using IDA Pro or Ghidra on the executable and trying to search for specific instruction patterns, because if I have to split this instruction into more than 2 opcodes, it is unlikely that they will be consecutive in the executable. @FAST6191 I saw your post regarding AArch64 ASM from 2022 in the Vita section, maybe you could weigh in? You seem to know your stuff.
P.S.: The 2 x86 opcodes that I am trying to convert are the following:
Code:
[rbx + 00000330], 3DA3D70A
[rbx + 0000034C], 00000002
Code:
C7 83 30 03 00 00 0A D7 A3 3D C7 83 4C 03 00 00 02 00 00 00
