R4 like Switch FPGA Code

[brawhalla1]

Note: this is work in progress, needs to be finished. Use for your risk


Even though other people already launching our r4 solutions i will share my progress developing a chip to emulate using FPGA Actel ProASIC 3 ASP250 VQG100 1115 ZA632076 (like r4 gold) for emulate bus signal from ROM (not xci image, just full rom dump) for switch cartridge (see https://switchbrew.org/wiki/Gamecard)

this is very simple on related a actual jailbreak solution

this just consists in emulate real cartridge chip like a real MMC using programmable fpga hardware.

If this work dumps will work like a genuine card.


FPGA Verilog Firmware:

module rom_controller (
input wire clk,
input wire rst,
input wire [31:0] signal,
output reg [31:0] data
);
output wire [15:0] spi_mosi;
input wire [15:0] spi_miso;
output wire spi_sck;
output wire spi_cs;
output wire [7:0] led;
sd_card sd_card (
.clk(clk),
.rst(rst),
.cs(spi_cs),
.mosi(spi_mosi),
.miso(spi_miso),
.sck(spi_sck)
);
top top (
.clk(clk),
.rst(rst),
.signal(signal)
// .data(data)
);
endmodule
module sd_card (
input wire clk,
input wire rst,
output wire cs,
input wire [15:0] mosi,
output wire [15:0] miso,
input wire sck
);
reg [7:0] data;
reg [7:0] byte_count;
parameter IDLE = 0;
parameter READ_CMD = 1;
parameter READ_DATA = 2;
parameter READ_STOP = 3;
reg [2:0] state;
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= IDLE;
byte_count <= 0;
end else begin
case (state)
IDLE: begin
if (cs) begin
state <= READ_CMD;
end
end
READ_CMD: begin
data <= mosi;
if (sck) begin
state <= READ_DATA;
end
end
READ_DATA: begin
data <= miso;
byte_count <= byte_count + 1;
if (byte_count == 8) begin
state <= READ_STOP;
end
end
READ_STOP: begin
if (sck) begin
state <= IDLE;
end
end
endcase
end
end
assign miso = data;
endmodule
module top (
input wire clk,
input wire rst,
input wire [31:0] signal,
input wire cs,
output reg [31:0] data
);
// ...
reg [31:0] file_bytes [0:MAX_FILE_COUNT-1];
reg [31:0] random_number;
reg [31:0] file_index_random;
reg [31:0] i;
reg [31:0] file_index;
wire [15:0] miso;

parameter MAX_FILE_COUNT = 100;
lfsr_random #(32) random_generator (
.clk(clk),
.rst(rst)
);
always @(posedge clk) begin
if (rst) begin
data <= 0;
end else begin
if (cs) begin
data <= file_bytes[file_index_random];
end
end
end
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < MAX_FILE_COUNT; i = i + 1) begin
file_bytes <= 0;
end
end else begin
if (cs) begin
file_bytes[file_index] <= miso;
file_index <= file_index + 1;
end
end
end
always @(posedge clk) begin
if (rst) begin
random_number <= 0;
end else begin
if (cs) begin
random_number <= random_generator.lfsr;
end
end
end
always @(posedge clk) begin
if (rst) begin
file_index_random <= 0;
end else begin
if (cs) begin
file_index_random <= random_number % MAX_FILE_COUNT;
end
end
end
always @(posedge clk) begin
if (rst) begin
data <= 0;
end else begin
if (cs) begin
data <= file_bytes[file_index_random];
end
end
end
endmodule
module lfsr_random #(
parameter DATA_WIDTH = 16
)(
input wire clk,
input wire rst,
output reg [DATA_WIDTH-1:0] random_number
);
reg [DATA_WIDTH-1:0] lfsr;
always @(posedge clk or posedge rst) begin
if (rst) begin
lfsr <= 16'h1234;
end else begin
lfsr <= {lfsr[DATA_WIDTH-2:0], lfsr[DATA_WIDTH-1]} ^ (lfsr << 1);
end
random_number <= lfsr;
end
endmodule

Build:

iverilog -o out rom_controller.v

FPGA Actel ProASIC 3 ASP250 VQG100 1115 ZA632076 datasheet: https://ww1.microchip.com/downloads...s/FPGA/ProductDocuments/UserGuides/pa3_ug.pdf
Winbond 25q155nsjc 1124 (SDCard IC) https://pdf1.alldatasheet.com/datasheet-pdf/view/555584/WINBOND/W25X40CLSNIG.html

3D Printable cardtridge case (after make pcb) https://www.printables.com/model/31474-nintendo-switch-cartridge

Pinout:

Pin	Module	Function
GND	All modules	Ground
CD#	All modules	Card Detect
CLK	All modules	Clock
RCLK	All modules	Return Clock
CS#	All modules	Chip Select
DAT[7:0]	All modules	Data Bus
VCC 3.1V	All modules	Power Supply (3.1V)
VCC 1.8V	All modules	Power Supply (1.8V)
RST#	All modules	Reset

Module Pintout:

Pin	Module
spi_mosi	sd_card
spi_miso	sd_card
spi_sck	sd_card
spi_cs	sd_card
clk	top, sd_card
rst	top, sd_card

Brazil carai

 

[linuxares]

Aight, anyone got soldering skills and a PCBWay account? x3

 

[ghjfdtg]

This doesn't do shit. It looks like something ChatGPT would spit out.

 

[bobmcjr]

This doesn't do shit. It looks like something ChatGPT would spit out.

I concur.
I'm loving the LFSR seeded with 0x1234 that selects what random index of data to spit out. And the top level bus widths aren't even correct.

 

[brawhalla1]

This doesn't do shit. It looks like something ChatGPT would spit out.

This is work in progress, but work. and not chatgpt. I think chatgpt cant do this. Some data secs need to be optimzed. The random data when vcc is came is for random game select, in the future this can be ordered by game name saving state in the sdcard

 

[linuxares]

This is work in progress, but work. and not chatgpt. I think chatgpt cant do this. Some data secs need to be optimzed. The random data when vcc is came is for random game select, in the future this can be ordered by game name saving state in the sdcard

Curiously, do you have a video of it working?

 

[Jayro]

Please make sure you get it right so Nintendo can't patch it out with an OS update. Or you'll have to make hardware revisions.

 

[TheStonedModder]

Note: this is work in progress, needs to be finished. Use for your risk


Even though other people already launching our r4 solutions i will share my progress developing a chip to emulate using FPGA Actel ProASIC 3 ASP250 VQG100 1115 ZA632076 (like r4 gold) for emulate bus signal from ROM (not xci image, just full rom dump) for switch cartridge (see https://switchbrew.org/wiki/Gamecard)

this is very simple on related a actual jailbreak solution

this just consists in emulate real cartridge chip like a real MMC using programmable fpga hardware.

If this work dumps will work like a genuine card.


FPGA Verilog Firmware:



Build:



FPGA Actel ProASIC 3 ASP250 VQG100 1115 ZA632076 datasheet: https://ww1.microchip.com/downloads...s/FPGA/ProductDocuments/UserGuides/pa3_ug.pdf
Winbond 25q155nsjc 1124 (SDCard IC) https://pdf1.alldatasheet.com/datasheet-pdf/view/555584/WINBOND/W25X40CLSNIG.html

3D Printable cardtridge case (after make pcb) https://www.printables.com/model/31474-nintendo-switch-cartridge

Pinout:

Pin	Module	Function
GND	All modules	Ground
CD#	All modules	Card Detect
CLK	All modules	Clock
RCLK	All modules	Return Clock
CS#	All modules	Chip Select
DAT[7:0]	All modules	Data Bus
VCC 3.1V	All modules	Power Supply (3.1V)
VCC 1.8V	All modules	Power Supply (1.8V)
RST#	All modules	Reset

Module Pintout:

Pin	Module
spi_mosi	sd_card
spi_miso	sd_card
spi_sck	sd_card
spi_cs	sd_card
clk	top, sd_card
rst	top, sd_card

Brazil carai

Well if anyone wants to test this and can’t print out their own case. I’m welcome to donate my printers time and filament

Paying a company to print an STL is usually hella expensive unless at scale