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According to the Intel roadmap, in late 2009 and early 2010 they will release a legendary processor called sandy bridge. The specs were as follows:
* 32 nm process.
* 8 "nodes"/processor.
o 4 cores/node (32 cores).
+ 4 threads/core (128 threads).
* 2 GHz clock speed or higher.
* 512 KB L2 cache/node.
* 3 MB last level cache/node (24 MB total).
* Ring bus that connects the last level caches.
* 2009-2010 release timeframe.
* A 15x performance improvement over the Xeon 5100.
* Aimed at Sun's UltraSPARC T1 and its successors.
* 4 GHz clock speed.
* 4 to 8 out-of-order cores.
* Without SSE: 8 DP GFLOPS/core (2 DP FP/clock), 32-64 DP GFLOPS/processor.
* With SSE: 28 DP GFLOPS/core (7 DP FP/clock), 112-224 DP GFLOPS/processor.
* 32 KB L1 cache/core, (3 clocks).
* 512 KB L2 cache/core, (9 clocks).
* 2-3 MB L3 cache/core (8-24 MB total) (33 clocks), most likely pooled and dynamically allocated among the cores.
* 64 bytes cache line width.
* 256 bytes/cycle Ring bus bandwidth. The ring bus connects the cores.
* 0-512 MB GDDR / fast DRAM.
* 64 GB/s GDDR / fast DRAM memory bandwidth.
* 17 GB/s memory bandwidth per QuickPath link with 50 ns latency.
I looked and this and I flipped, 32 cores and 128 threads with 24MB cache. 15X performance of one of the top performing current Xenon CPU by Intel. However, I doubt this guy will be too useful for gaming in even the next 6 or 7 years. Why can't graphics technology be as quick evolving as this? Every generation, the jump between GPU is so low that it is sad.... (Geforce 8800 and 9800) However, ATI seems to be doing an ACCEPTABLE job.
* 32 nm process.
* 8 "nodes"/processor.
o 4 cores/node (32 cores).
+ 4 threads/core (128 threads).
* 2 GHz clock speed or higher.
* 512 KB L2 cache/node.
* 3 MB last level cache/node (24 MB total).
* Ring bus that connects the last level caches.
* 2009-2010 release timeframe.
* A 15x performance improvement over the Xeon 5100.
* Aimed at Sun's UltraSPARC T1 and its successors.
* 4 GHz clock speed.
* 4 to 8 out-of-order cores.
* Without SSE: 8 DP GFLOPS/core (2 DP FP/clock), 32-64 DP GFLOPS/processor.
* With SSE: 28 DP GFLOPS/core (7 DP FP/clock), 112-224 DP GFLOPS/processor.
* 32 KB L1 cache/core, (3 clocks).
* 512 KB L2 cache/core, (9 clocks).
* 2-3 MB L3 cache/core (8-24 MB total) (33 clocks), most likely pooled and dynamically allocated among the cores.
* 64 bytes cache line width.
* 256 bytes/cycle Ring bus bandwidth. The ring bus connects the cores.
* 0-512 MB GDDR / fast DRAM.
* 64 GB/s GDDR / fast DRAM memory bandwidth.
* 17 GB/s memory bandwidth per QuickPath link with 50 ns latency.
I looked and this and I flipped, 32 cores and 128 threads with 24MB cache. 15X performance of one of the top performing current Xenon CPU by Intel. However, I doubt this guy will be too useful for gaming in even the next 6 or 7 years. Why can't graphics technology be as quick evolving as this? Every generation, the jump between GPU is so low that it is sad.... (Geforce 8800 and 9800) However, ATI seems to be doing an ACCEPTABLE job.







