The design is pretty simple, but I'm quite proud of it. its a modified sap-1 architecture, with the biggest difference being that it uses 12-bit words in memory (as opposed to 8-bit), and has a second, smaller bus (4-bit) that is only available to the instruction register & ram. (If my reasoning behind this isn't clear, Just tell me. I'll draw a diagram of it as well).
Currently, the amount of ram that I plan on using is 32 lines of 12-bit words (density of 384-bits, but only 256 are usable by main bus). I was't able to find a chip of this size, so instead I'm using a matrix of six 74LS189 chips.(note: I could add another ten 74LS189 chips for a total of 64 lines of 16-bit words, but this is unnecessary, and I would have to make a few changes to the instruction register.)
schematics of everything will be added to my github eventually.
wish me luck! and if you have any questions or suggestions I would love to hear them!
Currently, the amount of ram that I plan on using is 32 lines of 12-bit words (density of 384-bits, but only 256 are usable by main bus). I was't able to find a chip of this size, so instead I'm using a matrix of six 74LS189 chips.(note: I could add another ten 74LS189 chips for a total of 64 lines of 16-bit words, but this is unnecessary, and I would have to make a few changes to the instruction register.)
schematics of everything will be added to my github eventually.
wish me luck! and if you have any questions or suggestions I would love to hear them!
