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[SNEmulDS] Rebirth the project and update it for the last DKP
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<blockquote data-quote="Coto" data-source="post: 10323553" data-attributes="member: 255070"><p>Happy new year from Chile! México es país hermano! lml</p><p></p><p>SuperFX in DSi is not possible due to current Snes9X SuperFX being LLE (or a hackish LLE mixed with HLE).</p><p></p><p>1) SuperFX is 21.4Mhz so you can imagine the 1/10th cycle rule doesn't work @ 133mhz TWL CPU. 133 / 10 = 13mhz (a.k.a only theoretically SuperFX 1 HLE games could run full speed on TWL)</p><p></p><p>2) Keep in mind the SNES APU is 1.024Mhz(1024000khz), and an assembly core runs more or less fine on ARM7 @ 33mhz (the 1/10th cycle rule applies here) provided it's written in assembly only and only in assembly. So it runs full speed, and what actually SnemulDS does.</p><p>I've tried running C SPC700 core before in ARM7 and runs slow as hell, sort of like 3-4 samples per second @ 32000khz audio timer playback.</p><p></p><p>CX4, DSP and S-DD1 are HLE, hence they run (mostly) full speed on the NTR/TWL hardware as HLE is basically doing what the chip does abstracted in High Level and then compiled as native ARM code.</p></blockquote><p></p>
[QUOTE="Coto, post: 10323553, member: 255070"] Happy new year from Chile! México es país hermano! lml SuperFX in DSi is not possible due to current Snes9X SuperFX being LLE (or a hackish LLE mixed with HLE). 1) SuperFX is 21.4Mhz so you can imagine the 1/10th cycle rule doesn't work @ 133mhz TWL CPU. 133 / 10 = 13mhz (a.k.a only theoretically SuperFX 1 HLE games could run full speed on TWL) 2) Keep in mind the SNES APU is 1.024Mhz(1024000khz), and an assembly core runs more or less fine on ARM7 @ 33mhz (the 1/10th cycle rule applies here) provided it's written in assembly only and only in assembly. So it runs full speed, and what actually SnemulDS does. I've tried running C SPC700 core before in ARM7 and runs slow as hell, sort of like 3-4 samples per second @ 32000khz audio timer playback. CX4, DSP and S-DD1 are HLE, hence they run (mostly) full speed on the NTR/TWL hardware as HLE is basically doing what the chip does abstracted in High Level and then compiled as native ARM code. [/QUOTE]
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