I already did.
My main point is:
If you are already in a interrupt state that means waitstates-compatible memory can read/write such the ITCM/DTCM (
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0198e/Cihffjgb.html) thats all OK, but you still force an external interrupt (by using memory whose waitstates are way worse, or by programatically calling an external interrupt through a timer, ignoring the memory waitstates) you have one out of two possibilities:
1) poll the waitstate of target memory controller until the last hardware timer interrupt to frameHandler(); accesses it.
2) will sometimes cause the slower memory to force waitstates or override them, and if overriden, you will get lockups (not just because you move the frameHandler(); to itcm means the AHB bus will gracefully accept overriden waitstates told by the timer interrupt unless the above ARM Core setup)
This explains pretty well the AHB connections with DMA controllers, the processor is a newer one, but the design is kept as ive seen myself the frame differences when causing a dma controller copy from ewram/dtcm/itcm (those last two by reserving a .global buffer before) to vram async, against a ewram + timer copies, with the last one always causing lockups.
http://cliffle.com/article/2015/06/11/matrix/
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So my base point: setting a VBLANK handler, and when the frame is received/converted, use DMA to move on VBLANK to vram. this is how the AHB was constructed around somehow and the reason ninty I think decided to go with. Just a word of "why not just the design the DS has already".
I see you excluded as much as EWRAM as possible, by using static, the variables are set on stack (DTCM).
But like again i will say, whatever.