I'll have to do a timing analysis on my test ds. I think a logic analyzer aught to do the job.
Measure Vcc and /RESET, the rest aren't important for timing analysis*.
Vcc and /RESET should rise at the same time, then after 5ms or 27ms (I forgot) /RESET should go low for 1024 (or 4096 ?) cartridge cycles, then rise, then after maximum ~1.3ms (I didn't time it correctly) it will start spamming commands.
But yeah, I'd appreciate if you could do more precise timing analysis, that would be useful.
Here's the expected rundown:
- Vcc and /RESET rise at the same time, cartridge is in undefined state
- /RESET, /CS1, and /CS2 are pulled low, and it's clocked for 1024 (or 4096 ?) clock cycles
- /RESET, /CS1, and /CS2 are released
- almost immediately after, DS sends a BLOWFISH_PRELOAD (9F00000000000000) command
- after a little wait, DS sends some other commands, but it will eventually fail due to garbage results caused by floating data pins; measuring should end here, as the cartridge emulator must've already booted fully by this point
Note: you'll HAVE TO push in the cart detect pin (NOT the /IRQ pin) using the plastic shell of the cartridge (or like I did, solder it together, as my cart slot snapped off), otherwise it will be refused to detect at all.
* or at least in ntrboot mode, after a reset it immediately starts spamming commands as fast as possible after a reset, so it's a really good indicator